A variable delay line PLL for CPU-coprocessor synchronization

Abstract

A fully integrated phase-locked loop (PLL) is used to time-align the hi-Z/low-Z transitions of a CMOS CPU and its floating-point coprocessor (FPC), resulting in minimum timing difference (skew) between the two devices at their shared data bus, and decreasing the bus cycle time. The PLL circuit abandons the traditional voltage-controlled oscillator function, instead using a CMOS voltage-controlled delay line to improve noise immunity, ease loop stabilization, and permit dynamically adjustable clock periods. With the PLL enable, measured timing skew between the CPU and FPC is below 1 ns.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>