A validation methodology for real time model of modular multilevel converter

Abstract

Modular multilevel converter (MMC) is a promising topology for medium and high power applications. The MMC system consists a large number of sub-modules (SMs), which take long time to simulate. In a real-time simulator, the MMC model is optimized to have a fast simulation speed for real-time applications, such as hardware-in-the-loop (HIL) tests. The methodology to evaluate model fidelity is important. In this paper, a methodology is proposed to validate an MMC model capable of real time simulation and implemented in central processing unit (CPU) and field-programmable gate array (FPGA). The model is validated in both open-loop and closed-loop control in a simple MMC test system, and compared to a reference detailed model made with SimPowerSystems (SPS) blocks. The effect of the model sampling time on the accuracy is also studied. The results indicate the MMC model optimized for real time simulation with a time step of 25 μs is as accurate as an SPS model with a time step of 0.2 μs.