Abstract

The operating conditions of the High Luminosity upgrade of the Large Hadron Collider are very demanding for the design of next generation hybrid pixel readout chips in terms of particle rate, radiation level and data bandwidth. To this purpose, the RD53 Collaboration has developed for the ATLAS and CMS experiments a dedicated simulation and verification environment using industry-consolidated tools and methodologies, such as SystemVerilog and the Universal Verification Methodology (UVM). This paper presents how the so-called VEPIX53 environment has first guided the design of digital architectures, optimized for processing and buffering very high particle rates, and secondly how it has been reused for the functional verification of the first large scale demonstrator chip designed by the collaboration, which has recently been submitted.

Highlights

  • A Universal Verification Methodology (UVM) simulation environment for the study, optimization and verification of HL-LHC digital pixel readout chips

  • This paper presents how the so-called VEPIX53 environment has first guided the design of digital architectures, optimized for processing and buffering very high particle rates, and secondly how it has been reused for the functional verification of the first large scale demonstrator chip designed by the collaboration, which has recently been submitted

  • A UVM simulation and verification environment has been developed by the RD53 Collaboration

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Summary

Description of the VEPIX53 framework

The VEPIX53 framework, represented in figure 2, consists of a top level testbench which contains the DUT (wrapped in a top level harness module) and different UVM verification components (UVCs); these are instantiated and configured according to the test scenario, which is specified by the different tests that are run (defined in the test library). The input hits can be either generated in a constrained-random fashion, according to a set of pre-defined classes of clustered hits, or read from physics data in ROOT format produced by Monte Carlo pixel detector simulations. With reference to the Monte Carlo data, for the simulations described in this paper we have used CMS ROOT trees produced by a workflow based on the CMS data analysis framework (CMSSW) These data sets contain events related to layer 0 of the CMS pixel detector with different pixel sizes (50×50 or 25×100 μm, where the size is expressed as z×φ with reference to the cylindrical coordinate scheme of the pixel detector), sensor thickness of 150 μm, a digitizer threshold of 1500 e− and a pileup of 140. Subsets have been extracted related to modules at the center and edges of the barrel, i.e. with particles hitting the sensor at different angles, corresponding to different cluster sizes

Architecture study and optimization
Behavioral level study
RTL study
Architecture optimization into RD53A
40 MHz FE
Functional verification
Findings
Conclusion
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