A useful application of CMOS ternary logic to the realisation of asynchronous circuits

Abstract

This paper shows how the application of a CMOS ternary logic is useful in the realisation of delay insensitive (DI) asynchronous circuits. It is shown that fully DI asynchronous circuits are obtained with a ternary handshake protocol which employs the third logic level as idle state of the asynchronous interface. The advantages obtained are a dramatic reduction of the communication requirement and a lower power consumption as compared to other asynchronous solutions. It is then discussed how general purpose delay-insensitive circuits can be designed with ternary logic elements and finally an asynchronous sequence recognition circuit is described as an application of the approach.