A United Approach to Simulation and Timing Verification at the Functional Level

Abstract

This paper describes an integrated pair of tools - one designed for Timing Verification and the other designed for Logic Simulation - in a multi-level, mixed mode description environment.Historically, Logic Simulators and Timing Verifiers have been used for different types of verification, due to an inherent weakness in each. Particularly, Logic simulators have been weak in timing constraint checking, and Timing Verifiers in handling functional descriptions.An integrated Computer Aided Design system is described. Each tool in this integrated system is briefly presented. Then the problems normally encountered in Timing Verification at the functional level, as well as detailed timing analysis in Logic Simulators are described.A unified approach is presented to solve the difficulties presented above. First it is shown how the same description and the same set of support tools are shared by the two programs. An implementation of the timing constraint checking function, using special primitive elements is shown. Then it is shown how these primitives can be generated 'on the fly' from within a functional description, as well as in an interactive session through commands.