Abstract
The outline and the application results of a computer aided logic design system which combines automatic translation of TTL SSI/MSI logic into gate array logic, human intervention, auxiliary logic simulation, and automatic documentation are described. Automatic translation of logic circuit is done by macro expansion technique coupled with redundant logic reduction procedures.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
