A Unified VLSI architecture for 1D IDCT and IDST based on pseudo-band correlations

Abstract

In this paper an efficient unified VLSI architecture for the computation of 1-D IDCT and IDST that have been reformulated to be implemented on the same hardware structure with a minimum modification is presented. The proposed design is based on a new unified VLSI algorithm that can be used to compute both transforms. Using the proposed algorithm an efficient VLSI architecture has been obtained based on the systolic array architectural paradigm with a low hardware complexity and a low number of I/O channels placed at the two ends of the linear array and having a low I/O bandwidth. Moreover the proposed architecture is modular, regular and with local connection favoring a good VLSI implementation.