A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation

Abstract

This paper presents a unified Verilog-A compact model for lateral silicon nanowire field effect transistor (SiNW FET). The model incorporates all nanoscale effects including short channel effects, velocity saturation, mobility degradation, and quantization. Importantly, the model includes geometry dependent, TCAD calibrated, scalable parasitic capacitances and parasitic resistance models, which are dominant at highly scaled dimension. The model is well calibrated to generate the TCAD I-V and C-V characteristics for single and multiwire long, short channel devices. In addition, the model also reproduces I-V characteristics of the reported fabricated devices by different groups to a good accuracy, which underscores the accuracy of the model. Further using the compact model, the static and dynamic analysis of CMOS inverter with 15nm gate length is presented, which match well with TCAD simulations. Using this model the impact of device parasitic on circuit performance is studied by varying device extension length. The model is able to well predict the parasitic components for circuit performance, and is an important tool for design of NW based analog and digital circuits such as differential amplifier, current mirror, cell library and SRAM. The developed model is highly time efficient than TCAD simulator for NW based circuit simulations.