Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A Compact Model for Higher Performance

Abstract

In sub 10 nm technology node, vertical silicon nanowire (VNW) FET device has become a promising substitute due to its better gate controllability, short channel immunity, high ION/IOFF ratio and CMOS compatibility. This paper presents, a standard cell library using physics based Verilog-A compact model for 10 nm vertical SiNW FET device. A unified compact model included all the nanoscale effects (e.g. short channel effects, mobility degradation, velocity saturations etc.) as well as the parasitic capacitance and resistance model, which are highly dominant in lower technology nodes. The compact model is well matched with TCAD simulation data at 10 nm VNW FET device level. The cell library builds comprises of INVERTER, NAND, NOR and Ex-OR gate cells. Further, we compared the 10 nm VNW FET based standard cell performance to 45 nm bulk CMOS based standard cell library. It is found that the VNWFET based cells library design have an advantage of delay by ~4X and power consumption by ~14X against the 45 nm CMOS technology.