A Unified Interconnects Testing Scheme for 3D Integrated Circuits

Abstract

This paper proposed a full-chip testing scheme for 3D ICs to achieve the integrated horizontal/vertical interconnect reliability and yield enhancement with targets of interconnect faults under stuck-at and open fault models. This scheme is based on our previously developed IEEE std. 1500 compatible oscillation-ring (OR) testing methodology and further applies to Through-Silicon-Vias (TSVs)-based 3D ICs. The experimental results show that the both horizontal and vertical ring generation algorithms can achieve the optimal detectability for any interconnect. Compared with our previous work (IORT) in 2D ICs, the proposed HVOR needs only 43% extra rings for achieving 100% fault coverage in a 2-tier 3D ICs, and this work needs 82% testing time due to the concurrency characteristic in OR test scheme.