Abstract
—A 64Gbps 4-level pulse amplitude modulation (PAM4) mixed-signal receiver incorporating a decision-feedback equalizer (DFE) for application in wireline communication is implemented in fully-depleted silicon-on-insulator (FDSOI) 22nm technology. A two-stage slicer with body biasing is proposed to alleviate the stringent timing constraint of the closed-loop DFE. The smaller loading of the first stage shortens the output delay so as to provide a much larger differential input for the second stage. Moreover, body biasing is applied to the proposed slicer to allow higher drive and faster switching capabilities. Simulation results demonstrate that the receiver with body biased two-stage slicer achieves at least 9.9 % and 14.3 % improvements in recovered eye height and eye width over the receiver with StrongArm slicer. The receiver consumes a power of 117.1mW, achieving 1.83pJ/bit energy efficiency.
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