A Two-Step Analog Accumulator for CMOS TDI Image Sensor With Temporal Undersampling Exposure Method

Abstract

A two-step analog accumulator structure, fit for CMOS time-delay integration image sensor, is proposed to combat the impacts of parasitic phenomenon of the traditional one-step analog accumulator. To implement the two-step accumulation, the exposure signals are divided into groups. The synchronous signals in each group are integrated in step1 integrators, which are designed based on the switched-capacitor amplifier. Then, the integral signals from step1 are integrated in step2 integrators. The temporal undersampling exposure method is adopted in the sensor to reduce the number of integrators. Two versions of a prototype 64-stage two-step accumulator, with and without the decoupling capacitance $C_{d}$ , are designed and fabricated in 0.18- $\mu \text{m}$ one-poly four-metal 1.8 V/3.3 V CMOS technology. With an $8 \times 8$ stepping pattern, the signal-to-noise ratio improvements of the two versions are 17.278 and 17.192 dB at 64 stages, respectively, while the ideal value is 18.062 dB. The experimental results have proved the effectiveness of the two-step structure in combating the parasitic phenomenon and made the analog accumulator with higher stage realizable.