Abstract
This brief describes the design of a two-stage analog-to-digital converter (ADC) with voltage-controlled oscillator (VCO)-based second stage. The advantages of quantizing the first-stage residue in time domain versus traditional voltage domain are presented. The dc gain requirement of the first-stage residue amplifier is relaxed by reference-scaling and reference-recycling schemes. This enables the use of a very simple telescopic cascode amplifier in the gain stage. The second-stage VCO linearity is improved by a differential measurement of VCO frequency. Power consumption in the second stage is reduced by time-to-digital conversion for fine quantization of the VCO phase. Simulation results are presented for the design of a 13-bit 20-Msps ADC in 65-nm CMOS process. The estimated power dissipation of this converter is less than 1 mW.
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