A two-level cosimulation environment

Abstract

Hardware/software codesign seeks to integrate system level, hardware, and software design. Ideally, we would like tools that allow rapid evaluation of design decisions and a full exploration of the design space. Available tools are often too slow and concentrate on the low level cosimulation of hardware and software parts, after the design has been partitioned. We are attempting to remedy these problems with Tosca (Tools for System Codesign Automation), a hardware/software codesign environment. Targeted at single chip implementations consisting of a CPU core cell and dedicated hardware, Tosca performs a high level cosimulation for what-if analyses before hardware/software cosynthesis. After cosynthesis, Tosca generates simulatable software to be run on a retargetable instruction level model of the CPU. The software and hardware bound parts are then cosimulated using a commercial VHDL simulator. The performance of the low level cosimulation strategy and the high level simulator is remarkable. Low level cosimulation performance is about that of dedicated CPU software emulators-7200 pseudo assembly instructions per second. High level cosimulation is three times faster than the low level cosimulation. Both simulators allow functional debugging by interfacing to a commercial waveform visualizer (Mentor Graphics SimView). Engineers have used Tosca to redesign a commercial link controller.