A two-dimensional hardware design language for VLSI

Abstract

Hardware design languages which allow compile-time parameterization have had only limited success so far in getting user acceptance. A major stumbling block has been their one-dimensional nature. Designers prefer to represent the connectivity aspects of their designs in terms of pictures due to the two-dimensional nature of circuits. Therefore we propose a two-dimensional language for parameterized structural descriptions which is intended as graphical input language for a silicon compiler. This graphical language is useful for other applications which involve describing parameterized hierarchical directed graphs.