A trace-driven simulation study of two-level cache systems

Abstract

This paper presents a trace-driven simulation study to examine the performance of 2-level cache system using different combinations of replacement policies. The replacement schemes considered are: LRU-LRU, LRU-FIFO, FIFO-LRU and FIFO-FIFO. The address streams that drive the simulator were collected by a SUN SPARC-2 workstation running three different application programs: Fast Fourier Transform (FFT), Binary Search and Quick Sort application programs. The software tracing technique was used to collect address traces. It was found that the LRU-LRU replacement combination has the best performance followed by LRU-FIFO, FIFO-LRU and FIFO-FIFO, respectively. The simulation results have shown that for a fixed total memory size of the two caches, the larger the level-1 memory, the smaller the total effective access time, t eff, for the entire memory hierarchy. Finally, the performance of the two-level cache system was found to be more sensitive to the block(line)size variation than the number of sets variation.