A Time-Segmented Resonant Gate Driver Analysis for Loss, Speed, and SiC Switching Performance Trioptimization

Abstract

A novel “time-segmented” transient analysis approach is proposed in this article for resonant gate driver (RGD) with triaspect optimization. RGD is a more advanced solution in high-frequency and high-power-density applications than the conventional gate driver (CGD). RGD will achieve lower gate driver loss, faster driving speed, and better SiC switching characteristics. However, the majority of current works on RGD only focused on gate driver loss and ignored its effect on power transistors' switching behavior. The characteristics of RGD are not well understood and modeled due to the ignorance of nonlinear components, such as power transistor's nonlinear input capacitor and nonlinear resonant intervals, and driving resistances. All of those result in false estimation of switching time and energy, which will cause underdesign of gate driver power supply and overdesign of resonant inductor. To fully investigate the potential of RGD, a “time-segmented” analysis approach proposed in this article utilizes the second-order equivalent circuit with actual switching transients. Different equivalent input capacitors are adopted for each segment. The impacts of the resonant inductor and gate resistor are studied. An optimized resonant inductor design is summarized by considering the three aspects mentioned earlier. Based on these, a full-bridge series RGD is designed for SiC power transistors. Compared with CGD, RGD can realize a 25% reduction in power consumption and 75.5% faster driving time. The designed RGD also improves SiC's di/dt and dv/dt up to 32%.