A Time-Interleaved SAR Assisted Pipeline ADC With a Bias-Enhanced Ring Amplifier

Abstract

This brief presents a time-interleaved SAR assisted pipeline ADC with an inter-stage ring amplifier as an energy efficient structure. Ring amplifiers, an alternative to operational transconductance amplifiers, feature low power consumption and large output swing. Due to non-dominant poles in the three-stage structure, conventional ring amplifiers suffer from a bandwidth-limited settling. A bias-enhanced ring amplifier is proposed, which shifts non-dominant poles to higher frequencies and accelerates signal settling. In addition, a 1.5-bit per comparison scheme is adopted in the two time-interleaved SAR sub-ADCs to speed up the DAC settling of sub-ADCs. Prototyped in a 1.2-V 65-nm CMOS process, the 11-bit ADC achieves over 68.5-dB SFDR with a 2.4-MHz input, and a sample rate up to 250 MS/s while consuming 2.28 mW at 200 MS/s.