Abstract
A time-encoding machine (TEM) based new analog-to-digital converter (ADC) architecture is presented in this paper. The main advantage of this architecture is that it relies on asynchronous process and removes an important performance limiting factor in conventional ADCs: the clock jitter. Therefore, this architecture is suitable for very high speed ADCs. To expand the bandwidth coverage, the compressive sensing techniques is employed to reconstruct sparse signals with very high frequency. The system can run under two different modes: the normal mode where the signal is sampled at above Nyquist rate and the compressive sensing mode. Nonidealities in circuits and system parameter setting tradeoffs are analyzed to determine the best parameters for the system to reach optimal performance.
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