A threshold-embedded offset calibration technique for inverter-based flash ADCs

Abstract

A threshold-embedded offset calibration technique for inverter-based Analog to Digital Converter (ADC) is presented. Different from the conventional approach, this work uses a ratio-scaled digital CMOS inverter to define the comparison thresholds, and an extra voltage-controlled resistor is adopted to calibrate the threshold error caused by random mismatch variations. Moreover, a folding flash architecture is employed to reduce the number of inverters by half, which optimizes calibration effort and conversion power. The proposed threshold calibration technique is verified in a 5-bit 800MS/s flash ADC in 65-nm CMOS technology. After the calibration, the post layout simulations (PLS) show that the Effective Number of Bits (ENOB) can be significantly improved from 3.8 bits to 4.7 bits with the total power dissipation of 1mW and achieving a competitive Figure of Merit (FoM) of 48fJ/conv. The area of the whole ADC is 0.04mm2 only which included calibration circuits.