A New Architecture of Thermometer to Binary Decoder in a Low-Power 6-bit 1.5GS/s Flash ADC

Abstract

This paper introduces a new structure of the thermometer to binary decoder utilizing combination of two conventional approach and modify them in a low-power 6-bit flash analog to digital converter (ADC). Considering advantages of each method to form the presented decoder can lead to minimum possible power consumption which is a critical parameter in all converters especially in flash ADCs. Moreover, in the high-resolution flash ADCs, the decoder structure will be simpler compared to conventional ones and decreases the amount of power dissipation as well. Simulation results through HSPICE software level 49 parameters in 0.18μm standard CMOS technology parameters, prove the precise operation and the great improvements. The 6-bit converter achieves sampling rate of 1.5 GS/s, and precision of 5.10 effective number of bits (ENOB). The proposed ADC works with 1.8V power supply and it has the power consumption of 4.57mW and the figure of merit (FOM) is 0.047 pJ/conversion-step. Hence, this architecture would be dedicated to communication transceivers and data acquisition systems where area and energy efficiency are paramount.