Abstract
In this brief, we combine a buffered asymmetric dual-path structure with cascode Miller compensation to extend the unity-gain bandwidth of a three-stage amplifier while decreasing its power consumption. This design is implemented in a 65 nm CMOS technology with 0.0017 mm2 chip area and 6.62 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mu }\text{W}$ </tex-math></inline-formula> power consumption. Post-simulation results achieve <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${>}100$ </tex-math></inline-formula> dB DC gain, 1.20 MHz UGB, and 0.391 V/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mu }\text{s}$ </tex-math></inline-formula> SR with a 1.5 nF load capacitor.
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