A test structure advisor and a coupled, library-based test structure layout and testing environment

Abstract

A new test chip design environment, based on commercial tools, containing a test structure advisor and a coupled, library-based layout and testing environment has been developed. This environment results in a tenfold increase in productivity. The test structure advisor uses cross-sections of devices to recommend a comprehensive list of diagnostic and parametric test structures. These test structures can then be retrieved from the libraries of parameterized structures, customized, and placed in a design to rapidly generate customized test chips. Coupling the layout and test environments enables the automatic generation of a vast majority of the parametric test software. Using this environment, a new test chip, which would normally have taken over 1.5 weeks, was designed in 6 hours.