A Technology Based Complexity Model for Reversible Cuccaro Ripple-Carry Adder

Abstract

Quantum computing and circuits are of growing interest and so is reversible logic as it plays an important role in the synthesis of quantum circuits. Moreover, reversible logic provides an alternative to classical computing machines, that may overcome many of the power dissipation problems in the near future. In effect, the applied adiabatic signals are known to allow the signal energy stored on the various capacitances of the circuit to be redistributed rather than being dissipated as heat. They additionally avoid calculation errors introduced by the use of conventional rectangular pulses. Some ripple-carry adders based on a do-spy-undo structure have been designed and tested reversibly. This paper presents a simple complexity model taking into account some physical aspects of the technology, from the study of a cascade of Cuccaro adders processed in standard 0.35 mC MOS technology and used in true reversible calculation (computations being performed forwards and backwards such that addition and subtraction are made reversibly with the same chip), through both, simulations and experimental results. This paper provides a simple physical complexity model as basis for future cost models.