A Technique of Designing Low Leakage Latch-Type Sense Amplifier in Nanometer Technology

Abstract

The system on chip (SoC) application extensively uses SRAM memories. The SoC design demands that the leakage power consumed by the embedded SRAM should be as low as possible, especially at lower technology nodes. The reduction in leakage power of SRAM can be achieved by designing the bit cell and sense amplifier for low leakage. This paper proposes a low leakage voltage latched sense amplifier (VLSA) based on the source biased inverter Two additional transistors are employed in source biased inverter to mitigate the leakage current. The leakage power of the conventional inverter was found to be 27.668pW and for the source biased inverter it was 9.377pW. The source biased inverter provides 67% leakage power savings as compared to conventional inverter. The two conventional inverters of double switch PMOS access voltage latched sense amplifier (DSPA-VLSA) is replaced by the source biased inverter in 32nm CMOS technology. The leakage power of the conventional DSPA-VLSA was found to be 1.061nW and for the proposed VLSA it was 0.601nW.The low leakage sense amplifier proposed, provides a leakage power savings of 43.35%. The proposed sense amplifier also provides a sensing power savings of 20.57% and total power savings of 20.73% as compared to conventional DSPA-VLSA. The sensing delay of the proposed sense amplifier is comparable with the conventional design.