A technique for transparent fault injection and simulation in VHDL

Abstract

A technique is described for the automatic insertion of fault models into VHDL gate models, using shared variables and linked lists. This procedure does not require any modification to the structural description of a circuit using these models. This transparent fault modelling is illustrated using a netlist obtained from the synthesis of a VHDL RTL combinational logic circuit. A method for automatic sequential fault simulation is further demonstrated.