Abstract
Content Addressable memory (CAM) is a storage device which is widely implemented in the IP look-up table of a network router due to its high speed searching performance. In IPv6, the IP address will be 128 bits; as a result, the storage size of CAM will be larger in the future. The simulation time is an important factor affecting time-to-market. Using transistor level simulation such as SPICE in the early design stage of CAM will take huge time and delay time-to-market. SystemC is a system level modelling language and simulation platform; it provides better simulation efficiency and ability of hardware software co-design. However SystemC does not provide the function to estimate power consumption for low power algorithm or structure design. In this paper, we developed a SystemC CAM power estimation tool (SystemC CAM PET) to estimate match-line power of CAM in the early design stage. We construct a new CAM match-line power model to estimate match-line power consumption. We simulated ten benchmarks of Mibench and compared our SystemC CAM PET simulation results with SPICE simulation results. The simulation time is shorter in average 1654 and error rate of match-line power estimation is average 14.79%. In addition, our SystemC CAM PET is able to calculate the miss rate and the number of data comparison of each benchmark and PB-CAM structure.
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