A systematic reordering mechanism for on-chip networks using efficient congestion-aware method

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Abstract In-order delivery is a critical issue of memory parallelism in network-based MPSoCs where multiple memories can be accessed simultaneously. In addition to the in-order delivery, network congestion is another subtle point that required to be taken into account for such architectures. Therefore, a congestion-aware method is necessitated to deal with the network congestion while coping with the ordering of transactions. In this paper, we present a streamlined method, named Global Load Balancing (GLB), in order to reduce the network congestion. The ideas behind the GLB method are twofold. The first idea is to use the global congestion information as a metric for arbitration in routers to reduce the congestion level of highly congested areas. The second idea is to use an adaptive scheduler in network interfaces based on the global congestion information to avoid additional traffic to congested areas. Experimental results with synthetic test cases demonstrate that the on-chip network utilizing the GLB method considerably outperforms a conventional on-chip network.