A synchronous comparator architecture for the design of deadtimeless front-ends in high-rate pixellated detectors

Abstract

High-rate, pixelated detectors in present and future particle tracking applications call for advanced front-end circuits enabling the efficient readout of the signals delivered by the sensor. A compact, synchronous comparator enabling the integration of a zero dead time front-end is presented in this work. The proposed architecture is based on a clocked cascade of two common source stages followed by a couple of inverters. The circuit is virtually insensitive to process variations and mismatch and it is suitable for the development of flash-ADCs to be integrated in the elementary cell of a matrix of readout channels to be connected to the pixel sensor. The paper discusses the theory of operation of the proposed architecture and presents the main results coming from the simulation of the comparator in a commercial 28 nm CMOS technology.