Abstract
To achieve a higher conversion speed in an analog-to-digital converter (ADC), a modification to the successive approximation technique is proposed. In this, 2 b of digital output are approximated simultaneously instead of 1 b at a time. Simulations and layout of an A/D converter based on the proposed technique have shown an improvement in the conversion speed by a factor of about two while the increase in chip-area is about 25% only. The proposed technique does not affect the accuracy achievable with the successive approximation technique.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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