Abstract
A sub-sampling phase-locked loop (SSPLL) is presented to tolerate the supply interference and have a short re-locking time. A sampling phase detector, a voltage-to-current converter and a mini-dead zone creator are presented. The low in-band phase noise of the proposed SSPLL is kept and the power penalty is low. This SSPLL is realized in a 0.18µm CMOS process and its active area is 0.097mm2. The power consumption is 13.59mW from a 1.8V supply. At the output frequency of 2.2 GHz, this SSPLL achieves an in-band phase noise of -115.33dBc/Hz at 100kHz offset frequency with a division ratio of 44. Its root-mean-square jitter integrated from 10kHz to 100MHz is 0.77 ps.
Published Version
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call