A Sub-10 ps/gate Direct-Coupled FET Logic Circuit with 0.2 µm-Gate GaAs MESFET

Abstract

A 0.2 µm-gate buried p-layer metal semiconductor field-effect transistor (MESFET) using a new gate fabrication technique is reported. With this technique, the gate length can be easily reduced down to less than 0.2 µm. The source resistance of enhancement mode field-effect transistor (FET) can also be reduced, resulting in excellent DC and RF performance. The maximum transconductance of 648 mS/mm and K-value of 506 mS/V ·mm were obtained. The maximum cutoff frequency was as high as 96.1 GHz. The propagation delay time of 8.1 ps/gate was observed with a power dissipation of 1.7 mW/gate at a supply voltage of 1 V.