Abstract
In the power industry, hardware in-the-loop simulation (HILS) based on a real-time digital simulator (RTDS) is important technology for modular multilevel converter (MMC)-based high-voltage direct current (HVDC) power transmission. It is possible in real time to verify various fault situations that cannot be predicted by the software-in-the-loop simulation (SILS). This paper introduces the implementation methodology of sub-module (SM) capacitor voltage balancing for a MMC-HVDC physical control system based on field-programmable gate array (FPGA), which has the advantages of high-speed parallel operation and validates the reliability and accuracy of MMC-HVDC control when this control system is operated with RTDS. The characteristics of conventional capacitor voltage balancing methods, such as the nearest level control (NLC) with full sorting method, the NLC with reduced switching frequency method, and the tolerance band (TB) method, implemented on a physical control system based on this implementation methodology, are compared and analyzed. This paper proposes the improved capacitor voltage balancing method for MMC-HVDC transmission. Finally, the proposed capacitor voltage balancing method is compared with conventional methods to analyze performance in real-time to demonstrate that the proposed method is better than the conventional methods.
Highlights
The development of voltage source converter (VSC)-type high-voltage direct current (HVDC)transmission systems is becoming an important technology in the power transmission industry [1].Direct current (DC) transmission is economical because the insulation level of the line is low
The most commonly used band generation methods are the average tolerance band (ATB), for which the average value of the capacitor voltages is within the allowable range, and the cell tolerance band (CTB), for which the maximum value or minimum value of the capacitor voltages is within the allowable range
448 The proposed method appliesisthe average value of capacitor voltages like method comparedof the proposed method applies the average value of capacitor voltages like the method and compared
Summary
The development of voltage source converter (VSC)-type high-voltage direct current (HVDC). Direct current (DC) transmission is economical because the insulation level of the line is low It has the effect of dividing the power system and is advantageous in terms of power loss at long distances when compared to alternating current (AC) transmission. In order to construct the HILS for power converters, it is necessary to perform precise verification of each part while constructing the interface between the real-time simulator (e.g., RTDS or OPAL-RT). A low-level controller, such as modulation methods and capacitor voltage balancing methods, must be designed in consideration of the timing of the control logic because it must be implemented in the FPGA for high-speed parallel operation. The proposed new capacitor voltage balancing method is compared with conventional methods to analyze performance for a 240 MW and 1 GW-class MMC-HVDC system
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