A Study on Optimization of Planar Gate Type Metal-Oxide-Semiconductor Field-Effect-Transistors Multi Epitaxial Process in Super-Junction Structure

Abstract

Power metal-oxide-semiconductor field-effect-transistors (MOSFET) is a high voltage control device that requires high reliability and efficiency and is used to improve efficiency in areas such as renewable energy generators, electric vehicles, power supply unit, converters and motor control. Electrical characteristics of the MOSFET include a Threshold voltage which is a voltage for operating the device, an On-resistance which is a device resistance in an on-state, and a breakdown voltage which means a device withstand voltage. A Super-Junction structure is proposed to design the device with a high breakdown voltage and a low on-resistance. A multi-epitaxial Super-Junction MOSFET forms a Pillar layers by injecting continuously P-type impurity at edge on stacked N-Pillar layer. By forming the Pillar region which is higher doping concentration than N-drift, the on resistance can be reduced. In the forward blocking mode, the depletion layer of the Pillar region is extended to both vertical and horizontal sides, for a high breakdown voltage can be obtained. By using a T-CAD tool which is a process simulator, electrical characteristics of 1,200 V class super-junction MOSFET are analyzed along process variables (pillar lateral length, pillar concentration). When the breakdown voltage of the super junction MOSFET and the Planar MOSFET are equal, On-resistance (based on 10 A) has a gain of approximately 20% by a difference of 0.189 ohm×cm. It is believed that this can contribute to the development of super junction MOSFET with improved reliability and electrical characteristics.