Abstract
Drain junction breakdown in PMOSFETs can be due to any of the following leakages: 1.) subthreshold current; 2.) sub-surface punchthrough current; 3.) gate-induced drain leakage; or 4.) sub-surface band to band tunneling (diode leakage current). In this paper, the mechanism of gate-induced junction breakdown was experimentally characterized and studied. It can be explained through the theory of Gate-Induced Drain Leakage (GIDL) or surface band to band tunneling (BTBT). It was shown that gate-induced drain leakage has a direct correlation with the gate field applied and exhibits similar trend to the gate tunneling current. The magnitude of this leakage is affected by the electric field under the overlap region between gate and lightly-doped drain (LDD) structure as well as the amount of inversion charge at that region. Therefore, by optimizing the PLDD implant energy and dose, this gate-induced drain leakage can be minimized.
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