Abstract
The integrity of gate oxide shorts (GOS) model is a key factor as quality and reliability indicator of CMOS. Gate oxide defects in MOS transistors can be considered as the layout and technology dependent failures for which logic fault models are not always available, requiring electrical models to simulate the defect characteristics. Previously the GOS have been modeled with split transistors technique using two minor transistors and lumped elements. However, it is problematic to study minimum size transistors affected by GOS failures using the existing unidirectional split model as the channel length is designed at minimum size in particular technology process. This paper presents a study to compare and correlate between split model and non-split model of GOS.
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