A study of thin wafer handling in 3D-IC applications

Abstract

In order to uniformly expose Cu via, TSV wafer thinning becomes much critical contrary to conventional process. The complete wafer thinning process is expected composed of not only grinding, but also handling. This study develops advance wafer thinning process from temporary carrier bonding to carrier de-bonding that also includes grinding and backside processes. In this case, the bonded wafer thinning target is 100um for backside process. Void-free carrier bonding and bump after backside processes could be addressed. The carrier de-bonding process performs no wafer crack and residue. Moreover, whole wafer thinning process never suffers from Cu scratching. In this study, Under Bump Metallization (UBM) and bump were laid on the backside of Through Silicon Via (TSV) wafer. The wafers composed of various surface structures were carried out to bond glass carrier. The structure difference above came from various designs on UBM and bump. These designs may be backside UBM only, Redistribution Layer (RDL) + UBM, and even bumps on UBM. All the wafers were prepared through passivation patterning, sputtering, solder printing, plating and reflow. Among these processes, the wafer preparation also requires necessary passivation curing, sputtering for Cu seed deposition, and electroplating to form solder bump.