Abstract

In application-specific integrated circuit (ASIC) testing, the time consumed by DC parametric tests is much greater than that needed for functional tests, taking a significant part of the total testing time. A study on how to optimize DC parametric testing is presented. An optimal algorithm for selecting preconditioning addresses which results in an efficient use of automatic test equipment (ATE) is introduced. The idea is to minimize the total time spent using the parametric measurement unit, i.e., to do parallel measurement as much as possible. Benchmark results comparing this approach with a traditional method are presented. In addition, several key factors which affect the actual testing efficiency are discussed. Through the power of ATPG (automatic test pattern generation), not only is the speed of generating test programs increased, but the quality of the programs generated is improved. >

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