A Study of the Board Level Reliability of Large 16FF Wafer Level Package for RF Transceivers

Abstract

For mobile phone RF transceivers, wafer level packages (WLP) are a cost attractive solution allowing for minimum footprint and package height while providing good capability for routing and power delivery. The trend towards larger die sizes and smaller ball pitches leads to increasing reliability risks. Solder joint reliability can be improved by changing to Bi-doped solder ball alloys, but these increase the stress acting upon the fab back-end-of-line (BEOL)-stack. This is especially critical when in combination with fragile extreme low-K dielectrics (ELK). Board level underfill can solve the reliability challenge, but it comes at additional cost and process complexity. The reliability risks were assessed with full BEOL-stack test vehicles with up to 6.5 mm x 6.5 mm die size and solder ball pitch of 0.3 mm to match the upcoming RF transceiver generation or products for 5G. These test vehicles allow for a layer specific electrical detection of fails in the BEOL-stack with a good spatial resolution. By checking ESD-diodes, opens can be attributed to either BEOL-stack or to the connecting package structures. The test vehicle also comprises a daisy chain probing solder joint integrity and a die edge monitor. Temperature cycle on board (TCoB) results clearly show that SAC405 reliability is not sufficient for our large fine pitch WLP. Bi-doping improves solder joint reliability while on the other hand it leads to earlier fails in BEOL-stack and copper redistribution layers (RDL). The BEOL-stack via density turned out to be critical for the stack stability, so this parameter needs to be carefully controlled. Board level underfill resulted in excellent TCoB-performance, but both Bi-doped solder balls and board level underfill showed weaknesses in bend tests and mechanical shock tests. All these tradeoffs must be taken into account when defining the best solution for a given product.