A Study of Stacking Faults during CMOS Processing: Origin, Elimination and Contribution to Leakage

Abstract

An investigation of the generation of the stacking faults in silicon during the CMOS processing has been carried out using n‐type 2–5 Ω‐cm 7.5 cm diam (100) silicon wafers obtained from different manufacturers. Various thermal oxidation steps and the etching or cleaning steps preceding such oxidations were evaluated. It has been found: (a) Stacking faults were produced in densities of less than 1000/cm2 in 1050°C wet oxidations; (b) the p‐tub drive‐in generated stacking fault nuclei which grew into stacking faults (in densities of ≥104/cm2) during subsequent oxidations; (c) all stacking fault nucleation centers of type (b) and most of type (a) could be gettered by the presence of mechanical damage (such as the saw damage) on the back side of wafers, and densities ∼102/cm2 (a), and ∼0/cm2 (b) were found; (d) stacking faults thus formed contributed to leakage currents even when they appear not to be decorated with impurities. Various experiments leading to the above conclusions have been described and the results have been discussed. It is highly recommended that wafers with damaged back sides be used during processing in order to minimize the generation and growth of stacking faults and the leakage associated with such faults.