Abstract
Image placement (IP) and overlay error specifications are serious concerns for lithography at each successive technology node. Some of the primary contributors to image placement error (IPE) in EUV lithography are reticle and chuck surface non-flatness and chucking flatness non- uniformity. Flatness compensation has been proposed as a method to relax flatness specification for EUV substrates. However, in order for flatness compensation to work effectively, the various components of IPE i.e., reticle flattening and as-chucked z-height variation needs to be estimated accurately. Flatness compensation models assume a completely flat, rigid chuck and conformal clamping of the reticle backside. In this paper we will describe experiments designed to verify the different assumptions that the flatness compensation models are based on. The experiments involve printing wafers using a set of reticles of different flatness specifications on the ASML EUV Alpha Demo Tool (ADT) in Albany, NY. We will discuss results from these experiments and use Finite Element Modeling to simulate reticle chucking to correlate these results to physical properties electrostatic chuck on the ADT.
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