A study of Cu/Low-k stress-induced voiding at via bottom and its microstructure effect

Abstract

Microstructure effect of Cu/low-k interconnect, which is substantially affected by process condition or manufacturing deviation, is a dominated factors for copper stress and critical to the formation of stress-induced voiding (SIV). In this work, SIV at via bottom is studied in the aspects of thickness variation of copper interconnect and low-k dielectric. Besides, via-related factors consist of via profile and dimension are also involved in SIV sensitivity studies. With the assistance of finite element analysis (FEA), Cu stress in terms of different Cu/low-k microstructure scenarios are modelled to understand the voiding evolution and explore the their dependence with SIV susceptibility. Meanwhile, microstructure effects with and without redundant via are also simulated to evaluate their impacts on SIV immunity.