A structure definition technique for 25 nm lines of silicon and related materials

Abstract

This paper describes an interesting solution to integrate features with nanometer scale on silicon without using a special lithography tool. Simple layer deposition and etching processes fulfil the lithography demands of the SIA roadmap for the year 2012. This structure definition technique has been used to generate polysilicon gates, silicon oxide and nitride, aluminum, tungsten and titanium nitride lines down to 25 nm width with excellent homogencity over a 100 mm silicon wafer. It is transferable to any technology line, because only standard process steps like CVD deposition, dry and wet etching, and conventional optical lithography are necessary.