Abstract
Static phase offset (SPO) in conventional multiplying delay-locked loops (MDLLs) dramatically degrades the deterministic jitter performance. To overcome the issue, this paper presents a new SPO reduction technique for MDLLs. The technique is based on the observation that the SPO of MDLL is mainly caused by the non-idealities on charge pump (e.g. sink and source current mismatch), and control line (e.g. gate leakage of loop filter and voltage controlled delay line (VCDL) control circuit). With a high gain stage inserting between phase detector/phase frequency detector (PD/PFD) and charge pump, the equivalent SPO has been decreased by a factor equal to the gain of the gain stage. The effectiveness of the proposed technique is validated by a Simulink model of MDLL. The equivalent SPO is measured by the power level of reference spur.
Highlights
In high-speed data communication systems, on-chip clock multiplication plays a very important role
In Phaselocked loops (PLLs), Static phase offset (SPO) does not cause as much reference spur as multiplying delay locked loops (MDLLs) does because in PLL the reference edge does not replace the counterpart of voltage controlled oscillator (VCO) output
Where φSPO and τ are the phase and time domain static phase offset, Tref is the period of reference signal, Ileak is the leakage current on control line and ICP is the average charge pump current
Summary
In high-speed data communication systems, on-chip clock multiplication plays a very important role. Phaselocked loops (PLLs) and multiplying delay locked loops (MDLLs) are widely employed to generate the accurate high-frequency on-chip timing signals from a low frequency, low jitter clock source. A high-quality LC-tank oscillator can significantly reduce the effect of noise accumulation, it has a relatively small tuning range and occupies a large die area. This makes LC-tank VCO not the best candidate for data recovery and difficult to integrate. The reference spur performance of MDLL has been improved with all the reported SPO reduction techniques, it still cannot compare with that of PLL. To attempt to shorten the research gap, this work proposed a new SPO reduction technique that is inserting a gain stage between PD/PFD and charge pump to achieve lower equivalent SPO
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