Abstract
The paper describes a number of modifications to a standard phase frequency detector (PFD) that improve static phase offset (SPO) in both phase locked loops (PLLs) and multiplying delay locked loops (MDLLs). It then details a chopping methodology that eliminates SPO caused by timing mismatches in the PFD and charge pump (CP). The improvement that this method has on MDLL period jitter is also explained with supporting data from a 0.13 μm test chip.
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