Abstract
In this work the capability of TRAM (Transient Response Analysis Method) for detecting out-of-specification circuits is evaluated. With this purpose we adopt a behavioral point of view, defining a fault as the non compliment of any of the specifications. Although this approach has been previously addressed by many authors, this paper focuses on the usage of more precise simulation models to avoid assumptions of ideal behaviors. We have adopted for the assessment of this method a second order active filter of the State-Variable, implemented in a 180 nm CMOS commercial process with full-custom techniques. Also a methodology that injects random deviations in the circuit components has been considered for creating faulty and non-faulty circuits that will undergo the test.
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