A soft lithographic approach to fabricate InAs nanowire field-effect transistors

Sang Hwa Lee,Min Hyung Lee,Morten Madsen,Junghyo Nah,Kuniharu Takei,Sung-Ho Shin

doi:10.1038/s41598-018-21420-y

Abstract

The epitaxial layer transfer process was previously introduced to integrate high-quality and ultrathin III-V compound semiconductor layers on any substrate. However, this technique has limitation for fabrication of sub-micron nanoribbons due to the diffraction limit of photolithography. In order to overcome this limitation and scale down its width to sub-50 nm, we need either a costly short wavelength lithography system or a non-optical patterning method. In this work, high-quality III-V compound semiconductor nanowires were fabricated and integrated onto a Si/SiO2 substrate by a soft-lithography top-down approach and an epitaxial layer transfer process, using MBE-grown ultrathin InAs as a source wafer. The width of the InAs nanowires was controlled using solvent-assisted nanoscale embossing (SANE), descumming, and etching processes. By optimizing these processes, NWs with a width less than 50 nm were readily obtained. The InAs NWFETs prepared by our method demonstrate peak electron mobility of ~1600 cm2/Vs, indicating negligible material degradation during the SANE process.

Highlights

The scaling of Si-based metal-oxide-semiconductor field-effect transistors (MOSFETs) has played an important role in achieving high performance devices with low power consumption and has produced tremendous economic benefits[1,2]
The performance of III-V MOSFETs exceeds that of Si MOSFETs, high material costs and difficult integration of III-V materials onto conventional Si substrates have hindered the growth of III-V MOSFET industries
The epitaxial lift-off and transferring (ELT) technique was developed to integrate ultrathin III-V semiconductor layers onto Si/SiO2 substrate[13]

Summary

Introduction

The scaling of Si-based metal-oxide-semiconductor field-effect transistors (MOSFETs) has played an important role in achieving high performance devices with low power consumption and has produced tremendous economic benefits[1,2]. The epitaxial lift-off and transferring (ELT) technique was developed to integrate ultrathin III-V semiconductor layers onto Si/SiO2 substrate[13] This method allows facile integration of different III-V materials with huge lattice mismatches on the same substrate, which has been one of the main obstacles for their use in future device applications. Using this technique, high performance III-V MOSFETs, complementary metal-oxide-semiconductor (CMOS) logic circuits[14], and radio frequency (RF) circuits[15] on both Si/SiO2 substrates and flexible substrates have been demonstrated. Using the transferred NWs on a SiO2/Si substrate, InAs NWFETs were fabricated and exhibited high on/off current ratio (~104) and peak electron mobility (~1600 cm2V−1s−1), indicating that our approach is a reliable way to form one-dimensional nanomaterials from 2-D thin films

Methods

Results

Conclusion