Abstract
Design and performance of a single-chip minimum shift keying (MSK) coherent demodulator fabricated by complementary metal oxide semiconductor-integrated circuit (CMOS-IC) technology is described. The demodulator consists of a phase detection circuit, carrier recovery circuit, data recovery circuit, and timing-clock recovery circuit. For the carrier recovery circuit, three types of Costas-loop are reviewed from the viewpoint that MSK modulation format has a close relationship to binary phase shift keying (BPSK) and quadrature phase shift keying (QPSK). Among these loops, a loop of center-frequency locking scheme modified from a BPSK Costas-loop, termed MSK Costas-loop in this paper, is adopted for IC implementation. Digital IC design techniques are next described. Utilizing the sample-and-hold operation of the digital devices, a divided-frequency locking scheme of the quadrature coherent demodulation is proposed. Finally, IC demodulator performance is experimentally shown in the static and Rayleigh fading environments. The bit error rate performance and error-burst characteristic are measured. It is concluded that the single-chip coherent demodulator is suitable for digital mobile radio application.
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