A Single-chip DBS Tuner-Demodulator SoC using Discrete AGC, Continuous I/Q Correction and 200MS/s Pipeline ADCs

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A digital low-IF satellite TV tuner-demodulator SoC was realized in 0.13μm CMOS using low power 200MS/s eight bit pipeline ADCs. A discrete-steps delayed AGC loop using FET switched-resistors resulted in a 10dB noise figure at max gain and +25dBm IIP3 at min gain. The image rejection correction is continuously performed in the digital domain using an inverse gain and phase mismatch adjustment. A FFT engine was used for carrier/symbol rate estimation and channel blind scanning. SoC specifications include: 0.2dB implementation loss, <1.3°rms integrated phase noise,<-50dBc spurs, <0.2s channel acquisition time, 1.2W power dissipation from a dual 1.8/3.3V supply and 1.8x4.8mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die area.