A simulation-based analysis of effect of interface trap charges on dc and analog/HF performances of dielectric pocket SOI-Tunnel FET

Abstract

In this work, the impact of interface trap charges (ITCs) on electrical characteristics of dielectric pocket SOI-TFET (DP SOI-TFET) proposed for the reduction of ambipolar conduction and improvement of high-frequency (HF) performances has been demonstrated in details. The reliability of DP SOI-TFET has been examined by analysing the impact of varying polarity and density of ITCs on dc and analog/HF performances of the proposed device. Through TCAD simulations, it has been shown that donor and acceptor ITCs existing at the interface between drain region and dielectric pocket (i.e. Si/DP) have significant impact on the parameters such as OFF-state current, ambipolar conduction, parasitic capacitances, output resistance, and cut-off frequency of DP SOI-TFET. Furthermore, a comparative analysis has been carried out between the conventional and DP SOI-TFET under influence of traps, and it has been found that performances of the proposed device are further improved by the existence of acceptor ITCs at higher negatively biased gate. Even though, the existence of donor ITCs at Si/DP interface has been found degrading the performances of the proposed DP SOI-TFET, simulation results suggest that dc and analog/HF figure of merits are still superior in the proposed device as compared to those in the conventional SOI-TFET.